A typical LCD has the advantages of portability, low power consumption, and low radiation. Therefore, the LCD has been widely used in various portable information products, such as notebooks, personal digital assistant (PDA), video cameras, and the like. Furthermore, the LCD is considered by many to have the potential to completely replace cathode ray tube (CRT) monitors and televisions.
FIG. 4 is a schematic, abbreviated diagram of certain components of a conventional LCD. The LCD 10 includes a liquid crystal panel (not labeled), a gate driver 15, a data driver 16, and a timing control circuit 17 configured for controlling the gate driver 15 and the data driver 16.
The liquid crystal panel includes a plurality of gate lines 11 that are parallel to each other and that each extend along a first direction, a plurality of data lines 12 that are parallel to each other and that each extend along a second direction orthogonal to the first direction, and a plurality of pixel units (not labeled) defined by the intersecting gate lines 11 and data lines 12. The gate driver 15 is configured for driving the gate lines 11. The data driver 16 is configured for driving the data lines 12.
Referring also to FIG. 5, this is an enlarged circuit diagram of one pixel unit of the liquid crystal panel. A first gate line 111 and a second gate line 113 of the gate lines 11, together with two adjacent data lines 12, cooperatively define the pixel unit. The pixel unit includes a pixel electrode 103, a first common electrode 105, a second common electrode 106, and a thin film transistor 13. The pixel electrode 103, the first common electrode 105, and an insulating layer (not shown) therebetween cooperatively define a storage capacitor 101. The pixel electrode 103, the second common electrode 106, and the liquid crystal layer therebetween cooperatively define a liquid crystal capacitor 109. A source electrode (not labeled) of the thin film transistor 13 is electrically coupled to a corresponding data line 12. A gate electrode (not labeled) of the thin film transistor 13 is electrically coupled to the first gate line 111. A drain electrode (not labeled) of the thin film transistor 13 is electrically coupled to the pixel electrode 103.
Referring also to FIG. 6, this is a timing chart illustrating operation of the LCD 10. The gate driver 15 applies a plurality of gate signals G1-Gn to the gate lines 11. Each of the gate signals is a voltage pulse signal. The high level of the voltage pulse signal is Vgh, and the low level of the voltage pulse signal is Vg1. During each frame time T1, only one gate signal is applied to a corresponding gate line 11. Taking the first and second gate lines 111, 113 as an example, when the gate signal applied to the first gate line 111 is high, the thin film transistor 13 connected to the first gate line 111 is turned on. Data signal transmitted from the data line 12 is applied to the pixel electrode 103 via the thin film transistor 13. Thereby, a voltage difference is generated between the pixel electrode 103 and the first common electrode 105. The voltage difference charges up the storage capacitor 101. When the voltage of a next gate signal applied to the second gate line 113 is high, the voltage of the gate signal applied to the first gate line 111 is low. The thin film transistor 13 connected to the first gate line 111 is turned off. The storage capacitor 101 discharges to the liquid crystal capacitor 109 to maintain the voltage that is applied to the pixel electrode 103.
However, a parasitic capacitor 107 exists between the first gate line 111 and the pixel electrode 103. When the thin film transistor 13 is turned on, the total storage charge Q1 stored in the storage capacitor 101, the parasitic capacitor 107, and the liquid crystal capacitor 109 is expressed by the following equation:Q1=(Vgh−Vd1)*Cgd+(Vd1−Vcom)*(Clc+Cs)  (1)where Vd1 represents a voltage applied to the pixel electrode 103, Vcom represents a voltage applied to the first and second common electrodes 105, 106, and Cs, Cgd, Clc respectively represent the capacitances of the storage capacitor 101, the parasitic capacitor 107, and the liquid crystal capacitor 109.
When the thin film transistor 13 is turned off, the total storage charge Q2 stored in the storage capacitor 101, the parasitic capacitor 107, and the liquid crystal capacitor 109 is expressed by the following equation:Q2=(Vg1−Vd2)*Cgd+(Vd2−Vcom)*(Clc+Cs)  (2)where Vd2 represents a voltage applied to the pixel electrode 103. According to the principle of charge conservation, the total storage charge Q2 is equal to Q1. This is expressed by the following equation:(Vgh−Vd1)*Cgd+(Vd1−Vcom)*(Clc+Cs)=(Vg1−Vd2)*Cgd+(Vd2−Vcom)*(Clc+Cs)  (3)At the instant that the thin film transistor 13 is turned off, a feed through voltage ΔV applied to the pixel electrode 103 is expressed by the following equation:
                              Δ          ⁢                                          ⁢          V                =                                            Vd              ⁢                                                          ⁢              1                        -                          Vd              ⁢                                                          ⁢              2                                =                                                                      (                                      Vgh                    -                    Vgl                                    )                                *                Cgd                                            Cgd                +                Clc                +                Cs                                      .                                              (        4        )            
Because the capacitances Cs, Cgd, Clc of the storage capacitor 101, the parasitic capacitor 107, and the liquid crystal capacitor 109 are constant values, the feed through voltage ΔV is only determined by the voltage difference Vgh−Vg1. Typically, the capacitance Cs of the storage capacitor 101 is equal to 0.5 pF (pico-farad), the capacitance Cgd of the parasitic capacitor 107 is equal to 0.05 pF, and the capacitance Clc of the liquid crystal capacitor 109 is equal to 0.1 pF. The voltage difference Vgh−Vg1 is typically equal to 35 V (volts). Therefore, using equation (4), the value of the feed through voltage ΔV applied to the pixel electrode 103 is calculated as follows:
                              Δ          ⁢                                          ⁢          V                =                                            35              ×              0.05                                      0.05              +              0.1              +              0.5                                =                      2.69            ⁢                                                  ⁢            V                                              (        5        )            Typically, the voltage difference between two successive gray levels of the LCD 10 is in the range from 30 mV (millivolts) to 50 mV. When the thin film transistor 13 is turned on or turned off, the feed through voltage ΔV applied to the pixel electrode 103 is much greater than the voltage difference between two successive gray levels. As a result, the human eye can easily perceive flickering of images displayed by the LCD 10. That is, the display characteristics and performance of the LCD 10 are reduced.
What is needed, therefore, is an LCD and a driving method for driving the LCD which can overcome the above-described deficiencies.